VLSI design techniques in teaching and research

Digital design methods and practice have undergone some notable changes in recent years. Reliance upon traditional circuit design methods, such as schematic capture, has given way to the new approach of VHDL and logic synthesis. Most recently of all, one has witnessed the arrival of CASE-tool methodology for logic design, which integrates formalised schematic models with VHDL and synthesisable circuit descriptions. In academia, access to such tools tends to lag slightly behind the latest developments, but nonetheless, the opportunity to expose undergraduates to such leading-edge design methods is one that is both challenging and rewarding. At the University of Teesside, the Division of Electronic and Computer Engineering has applied new digital design tools in the domains of research, and teaching with successful results. In research we have applied VHDL and logic synthesis to the investigation and implementation of a 32-bit stack-oriented microprocessor architecture, and investigated the feasibility of neural implementations in silicon. Practising our philosophy of fuelling teaching content from research activities, we have introduced VHDL as part of the 2nd and final year honours degree curriculum, and present students with the task of developing a simple microprocessor core in VHDL, which they then synthesise with various process technologies and optimisation parameters. In this paper the authors present an informal review of VLSI design techniques applied in research, and how this has been integrated with teaching within their division. The intention is to give a view of what may be achieved in an academic setting and how postgraduate research has benefited the undergraduate learning experience