DocumentCode
2919258
Title
HW/SW TQ/IQT design for H.264/AVC
Author
Ben Atitallah, A. ; Loukil, H. ; Masmoudi, N.
Author_Institution
High Inst. of Electron. & Commun., Univ. of Sfax, Sfax, Tunisia
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
13
Lastpage
16
Abstract
In this paper, we present a HW/SW design for transform and quantization blocks to be used in the H.264/AVC prediction modes. The design is described in VHDL language and synthesized to Altera Stratix II FPGA and to TSMC 0.18μm standard-cells. In addition, a SoPC implementation and validation of the proposed design as an IP core is presented using the embedded FPGA development board.
Keywords
data compression; field programmable gate arrays; hardware description languages; system-on-chip; transforms; video coding; Altera Stratix II FPGA; H.264-AVC prediction mode; HW-SW TQ-IQT design; IP core; SoPC implementation; TSMC standard-cell; VHDL language; embedded FPGA development board; inverse quantization and transformation; size 0.18 mum; system on a programmable chip implementation; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Quantization; Throughput; Transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location
Beirut
Print_ISBN
978-1-4577-1845-8
Electronic_ISBN
978-1-4577-1844-1
Type
conf
DOI
10.1109/ICECS.2011.6122202
Filename
6122202
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