DocumentCode
2919314
Title
A 1.3mW CMOS 65nm 4th order 52dB-DR continuous-time analog filter for DVB-T receivers
Author
De Matteis, M. ; Cocciolo, G. ; De Blasi, M. ; Baschirotto, A.
Author_Institution
Innovation Eng. Dept., Univ. of Salento, Salento, Italy
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
21
Lastpage
24
Abstract
In this paper a 8.2MHz-f@-3dB bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a VDD/VTH ratio (supply/threshold voltage) as low as 2. Operating point issues due to low VDD/VTH ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance have been studied and considered in the design. Power consumption is minimized by using a novel algorithm based on Matlab procedure, which guarantees the minimum power consumption for a given transfer function, noise and linearity requirements. The device consumes 1.3mW from a single 1.2V supply voltage, features -10dBm-IIP3 at 32dB pass-band Gain, and 1.6mVrms output integrated noise over the pass-band (300kHz÷8.2MHz).
Keywords
CMOS analogue integrated circuits; HF amplifiers; radio receivers; radiofrequency filters; transfer functions; CMOS fourth order-DR continuous-time analog filter; CMOS node; DVB-T RX chain; DVB-T receivers; bandwidth 8.2 MHz; bias circuit; filter circuit; gain 32 dB; linearity requirements; power 1.3 mW; power consumption; size 65 nm; transfer function; voltage 1.2 V; voltage 1.6 mV; CMOS integrated circuits; CMOS technology; Linearity; Noise; Power demand; Receivers; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location
Beirut
Print_ISBN
978-1-4577-1845-8
Electronic_ISBN
978-1-4577-1844-1
Type
conf
DOI
10.1109/ICECS.2011.6122204
Filename
6122204
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