Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system

Author

Devlin, Benjamin ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan

fYear

2011

fDate

11-14 Dec. 2011

Firstpage

53

Lastpage

56

Abstract

In this paper we present an autonomous watchdog circuit for error robustness which can detect logic errors caused by power supply noises and soft errors, with the smallest overheads compared to current research. The proposed watchdog circuit is realized with the dual-pipeline self synchronous system, without the need to duplicate logic. The watchdog circuit prevents error propagation through the logic chain, and errors are successfully detected. Error tolerance to power supply bounce is measured at 67% at 1.2V. Circuit size and energy-per-operation is increased 6.9% and 16% respectivley for the case of a 65nm self synchronous FPGA.

Keywords

field programmable gate arrays; integrated circuit noise; radiation hardening (electronics); dual-pipeline self synchronous system; error propagation propagation; error robustness; error tolerance; gate-level autonomous watchdog circuit; logic error detection; power supply bounce measurement; power supply noise; self synchronous FPGA; size 65 nm; soft error; Delay; Logic gates; Noise; Pipelines; Power supplies; Robustness; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Conference_Location

Beirut

Print_ISBN

978-1-4577-1845-8

Electronic_ISBN

978-1-4577-1844-1

Type

conf

DOI

10.1109/ICECS.2011.6122212

Filename

6122212