Title :
Model-based design and distributed implementation of bus arbiter for multiprocessors
Author :
Ben-Hafaiedh, Imene ; Graf, Susanne ; Jaber, Mohamad
Author_Institution :
VERIMAG, UJF, Gieres, France
Abstract :
The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.
Keywords :
asynchronous circuits; logic design; microprocessor chips; protocols; abstract model; arbitration protocols; bus arbiter; high-level distributed model; model-based design; multiprocessors; Analytical models; Computer architecture; Performance evaluation; Program processors; Protocols; System recovery; System-on-a-chip;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
DOI :
10.1109/ICECS.2011.6122215
