Title :
A fault injection analysis of Virtex FPGA TMR design methodology
Author :
Lima, F. ; Carmichael, C. ; Fabula, J. ; Padovani, R. ; Reis, R.
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
This paper presents the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design. Each programmable bit upset able to cause an error in the TMR design has been investigated. Final conclusion using the TMR "golden" comparison method shows that "no errors" were reported by Virtex TMR design implementation in the presence of single bit upsets in the customization logic. The proton radiation ground test has confirmed the results achieved by fault injection.
Keywords :
SRAM chips; fault simulation; field programmable gate arrays; integrated circuit reliability; proton effects; redundancy; space vehicle electronics; SRAM-based FPGA; TMR golden comparison method; Virtex FPGA TMR design methodology; field programmable gate arrays; proton radiation; single bit upset fault injection analysis; spacecraft electronics; triple modular redundancy; CMOS process; Circuit faults; Design methodology; Error correction; Field programmable gate arrays; Logic devices; Protons; Redundancy; Testing; Voting;
Conference_Titel :
Radiation and Its Effects on Components and Systems, 2001. 6th European Conference on
Print_ISBN :
0-7803-7313-8
DOI :
10.1109/RADECS.2001.1159293
