Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers

Author

Tonelli, Matteo ; Boni, Andrea ; Azzolini, Cristiano

Author_Institution

Univ. of Parma, Parma, Italy

fYear

2009

fDate

12-17 July 2009

Firstpage

344

Lastpage

347

Abstract

A 1Gs/s CMOS track-and-hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65 nm low-power CMOS process, exhibits a total harmonic distortion lower than -80 dB and a spurious free dynamic range better than 79 dB, with a power consumption lower than 11 mW (dual supply voltages 1.2 V/2.5 V, 1.85 mA/4.22 mA).

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; harmonic distortion; local area networks; low-power electronics; receivers; sample and hold circuits; 10GBASE-T Ethernet receivers; current 1.85 mA; current 4.22 mA; high-speed switch; input buffer; low-power CMOS process; open-loop track-and-hold; size 65 nm; time-interleaved analog-to-digital converter; total harmonic distortion; voltage 1.2 V; voltage 2.5 V; Analog-digital conversion; CMOS process; Copper; Ethernet networks; MOS devices; Pipelines; Sampling methods; Signal resolution; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.

Conference_Location

Cork

Print_ISBN

978-1-4244-3733-7

Electronic_ISBN

978-1-4244-3734-4

Type

conf

DOI

10.1109/RME.2009.5201306

Filename

5201306