Design of high gain CMOS LNA with improved linearity using modified derivative superposition

Author

Zavarei, Mohammad Javad ; Kargaran, Ehsan ; Nabovati, Hooman

Author_Institution

Dept. of Electr. Eng., Sadjad Inst. for Higher Educ., Mashhad, Iran

fYear

2011

fDate

11-14 Dec. 2011

Firstpage

322

Lastpage

325

Abstract

This paper presents a highly-linear high-gain low noise amplifier (LNA) based on the inter stage technique. The linearized LNA is achieved by using the linear cascode amplifier as output stage utilizing a modified derivative superposition method and functionality is analyzed using Volterra series. Using simulations in 0.18μm CMOS technology, the IIP₃ is improved by more than 37dBm reaching to +3dBm, with the cost of decrease 10dB gain at 5.7GHz frequency band. The LNA consumes 18.7mW power under 1.8V supply voltage. Compared to previously published LNA designs, the proposed LNA has the smallest noise figure of 2.1 dB, highest gain 21.5 dB, and the highest Figure of Merit of 3.15.

Keywords

CMOS integrated circuits; Volterra series; field effect MMIC; low noise amplifiers; microwave amplifiers; CMOS LNA; CMOS technology; Volterra series; frequency 5.7 GHz; high-gain low noise amplifier; highly-linear low noise amplifier; inter stage technique; linear cascode amplifier; linearized LNA; modified derivative superposition; power 18.7 mW; size 0.18 mum; voltage 1.8 V; CMOS integrated circuits; Capacitance; Gain; Logic gates; Low-noise amplifiers; Noise figure; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Conference_Location

Beirut

Print_ISBN

978-1-4577-1845-8

Electronic_ISBN

978-1-4577-1844-1

Type

conf

DOI

10.1109/ICECS.2011.6122278

Filename

6122278