DocumentCode
2920953
Title
FPGA-based programmable digital PLL with very high frequency resolution
Author
Bouloc, J. ; Nony, L. ; Loppacher, C. ; Rahajandraibe, W. ; Bocquet, F. ; Zaid, L.
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
370
Lastpage
373
Abstract
A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.
Keywords
field programmable gate arrays; phase locked loops; FPGA-based programmable digital PLL; FPGA-based tunable all-digital control system; QuartusII; frequency 20 kHz to 60 MHz; high resolution all-digital PLL; phase-locked loops; very high frequency resolution; Finite impulse response filter; Force; Frequency control; Frequency modulation; Phase locked loops; Resonant frequency; AFM; DDSS; FPGA; Fast prototyping; high precision; instrumentation; phase locked loop;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location
Beirut
Print_ISBN
978-1-4577-1845-8
Electronic_ISBN
978-1-4577-1844-1
Type
conf
DOI
10.1109/ICECS.2011.6122290
Filename
6122290
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