DocumentCode :
2921103
Title :
A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS
Author :
Segundo, Jokin ; Arias, Jesús ; Quintanilla, Luis ; Enríquez, Lourdes ; Hernández, Jesús M. ; Vicente, José
Author_Institution :
Dept. de Electr. y Electron., Univ. of Valladolid, Valladolid, Spain
fYear :
2011
fDate :
11-14 Dec. 2011
Firstpage :
406
Lastpage :
409
Abstract :
The design and implementation in a 1.2 V, 130 nm CMOS technology of an ADC intended for OFDM UWB signals is described. This ADC is based on parallel, continuous-time ΣΔ modulators, and employs an OFDM-optimized NTF, implemented using a 3rd order lowpass and a 4t order bandpass modulator. Both are CRFB structures which use active-RC integrators. “Early DAC” clocking is used to reduce the GBW of opamps. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation.
Keywords :
CMOS integrated circuits; OFDM modulation; band-pass filters; continuous time filters; low-pass filters; quadrature phase shift keying; radio receivers; sigma-delta modulation; transfer functions; ultra wideband communication; 3rd order lowpass modulator; 4th order bandpass modulator; CMOS technology; GBW; OFDM UWB receivers; OFDM-optimized NTF; QPSK modulation; active-RC integrators; continuous-time ΔΣ based ADC; gain bandwidth product; layout-level simulation; noise transfer function; size 130 nm; system-level simulation; voltage 1.2 V; Clocks; Frequency measurement; Frequency modulation; Integrated circuit modeling; Noise; OFDM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
Type :
conf
DOI :
10.1109/ICECS.2011.6122299
Filename :
6122299
Link To Document :
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