DocumentCode
2921111
Title
Design of an 8Gsps, 65nm CMOS wideband flash ADC
Author
Mattos, D. ; Gauffre, S. ; Hellmuth, P. ; Caïs, P. ; Pedroza, J.-L. ; Bégueret, J-B ; Baudry, A.
Author_Institution
IMS Lab., Univ. of Bordeaux, Talence, France
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
410
Lastpage
413
Abstract
This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. The circuit has been fabricated with the 65nm CMOS technology from STMicroelectronics. The post-layout simulations show a Figure of Merit (FoM) of 11.36pJ/conv.step and a power consumption of 480mW at Nyquist sampling condition. The ongoing tests will soon verify these predictions.
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; sample and hold circuits; CMOS wideband flash ADC; analog-to-digital converter; demultiplexer; size 65 nm; track-and-hold; wideband radio astronomy applications; CMOS integrated circuits; CMOS technology; Clocks; Synchronization; Transistors; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location
Beirut
Print_ISBN
978-1-4577-1845-8
Electronic_ISBN
978-1-4577-1844-1
Type
conf
DOI
10.1109/ICECS.2011.6122300
Filename
6122300
Link To Document