A hardware efficient chaotic ring oscillator based true random number generator

In this work, we present a hardware efficient chaotic ring oscillator based true random number generator in multiple oscillator sampling topology. Recently introduced ring oscillator based true random number generators use significant number of rings for accumulating available jitter to a useful level. They require large silicon area and consume considerable amount of power dissipation whereas, the proposed circuit can boost jitter by a factor of 178 with only a few components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages over conventional designs. Random numbers generated by the proof of concept prototype passed all NIST statistical tests without any post processing.