• DocumentCode
    2921443
  • Title

    Experimental validation of a novel chaotic circuit for true random binary digit generation in cryptographic module application

  • Author

    Blaszczyk, Marta ; Guinee, Richard A.

  • Author_Institution
    Dept. of Electr. Eng., Cork Inst. of Technol., Cork, Ireland
  • fYear
    2009
  • fDate
    12-17 July 2009
  • Firstpage
    236
  • Lastpage
    239
  • Abstract
    In this paper the experimental validation of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on a chaotic circuit for nonlinear operation leading to stochastic like behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been first modeled in PSpice software and its state space formulation was implemented in Matlab and Simulink software to gauge simulation accuracy and potential as a cryptographic module via statistical testing. The randomness attributes of the modified generator, obtained from both the PSpice state space model along with the hardware implementation, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test Set for statistical validation. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed confirming theoretical expectations.
  • Keywords
    binary sequences; chaos; cryptography; random number generation; statistical testing; PRBSG topology; correlated binary sequence; cryptographic module application; double scroll attractor; double scroll chaotic attractor circuit; experimental validation; nonlinear operation; pseudorandom binary sequence generator; true random binary digit generation; true random binary generator; Binary sequences; Chaos; Circuit simulation; Circuit topology; Cryptography; Mathematical model; State-space methods; Statistical analysis; Stochastic processes; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.
  • Conference_Location
    Cork
  • Print_ISBN
    978-1-4244-3733-7
  • Electronic_ISBN
    978-1-4244-3734-4
  • Type

    conf

  • DOI
    10.1109/RME.2009.5201338
  • Filename
    5201338