Fault-Tolerant Verification Platform for Systems Modeled at High Level of Abstraction

As system-on-chip (SoC) becomes more and more complicated, and contains a large number of transistors, the SoC could encounter the reliability problem due to the increased likelihood of faults or radiation-induced soft errors when the chip fabrication enters the deep submicron technology. Thus, it is essential to employ the fault-tolerant techniques in the design of SoC to guarantee a high operational reliability in critical applications. An important issue in the design of fault-robust SoC is how to validate the robustness of the systems as early in the development phase to reduce the re-design cost. The goal of this study is to propose a new fault-tolerant verification approach based on a high-level abstract system model that can significantly reduce the validation efforts. The fault-tolerant verification platform proposed here can save the time of detailed hardware implementation, benchmark program development, and fault injection campaigns. As a result, it is efficient to reduce the implementation efforts and simulation time. However, since our approach employs a high level of abstraction to model the fault-robust systems, the accuracy of the simulation results will decrease. A fault-tolerant VLIW core developed by our team is used to demonstrate the feasibility of our approach by comparing the results obtained from this approach with the results derived from the simulation-based fault injection technique by VHDL.