Memory controller for globally uncoordinated and locally coordinated checkpointing

In order to deal with soft errors that affect the logic of multiprocessors, a new architecture with backward error recovery capability is proposed. The proposed architecture uses the fault containment capability offered by memory protection units for reducing the overhead due to the checkpointing information management. A new hybrid checkpointing scheme is proposed that aims at performing coordinated checkpointing on logic data sets that are built on software ensembles that logically interact. A new memory controller able to manage the checkpointing information is proposed for this architecture. It has been designed for minimizing the performance overhead for error-free scenarios. The performance and memory overhead have been evaluated for different applications.