Title :
A Simulink Model for All-Digital-Phase-Locked-Loop
Author :
Wang, Xiaoyan ; Choi, Yeung Bun ; Je, Mingkyu ; Yeoh, Wooi Gan
Author_Institution :
Inst. of Microelectron., Singapore
Abstract :
A Simulink model for all-digital-phase-locked-look (ADPLL) is proposed in this paper. The study is based on ADPLL implemented in an all-digital RF transceiver. Simulation results in Simulink give the performance overview of the ADPLL.
Keywords :
digital phase locked loops; logic simulation; transceivers; all-digital RF transceiver; all-digital-phase-locked-loop; simulink model; Capacitance; Circuit simulation; Digital circuits; Integrated circuit modeling; Mathematical model; Phase detection; Phase locked loops; Radio frequency; Transceivers; Tuning;
Conference_Titel :
Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on
Conference_Location :
Rasa Sentosa Resort
Print_ISBN :
978-1-4244-1307-2
Electronic_ISBN :
978-1-4244-1308-9
DOI :
10.1109/RFIT.2007.4443922
