A wide-frequency-range fractional-N synthesizer for clock generation in 65nm CMOS

Author

Zhang, Ye ; Zimmermann, Niklas ; Wunderlich, Ralf ; Heinen, Stefan

Author_Institution

Dept. of Integrated Analog Circuits & RF Syst., RWTH Aachen Univ., Aachen, Germany

fYear

2011

fDate

11-14 Dec. 2011

Firstpage

571

Lastpage

574

Abstract

In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of -107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF oscillators; delta-sigma modulation; field effect integrated circuits; frequency synthesizers; voltage-controlled oscillators; CMOS integrated circuit; adaptive controlled architecture; clock generation; delta-sigma modulation; frequency 600 MHz to 1.2 GHz; ring oscillator; size 65 nm; wide frequency range fractional N synthesizer; Clocks; Frequency conversion; Frequency modulation; Frequency synthesizers; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Conference_Location

Beirut

Print_ISBN

978-1-4577-1845-8

Electronic_ISBN

978-1-4577-1844-1

Type

conf

DOI

10.1109/ICECS.2011.6122339

Filename

6122339