DocumentCode :
2921934
Title :
Table of contents
fYear :
2007
fDate :
11-12 June 2007
Abstract :
The following topics are dealt with: IC layouts proximity correction; model-based layout optimization; silicon lattice damage measurement; embedded mechanical stress sensors; E-beam inspection methodology; backside wafer damage induced wafer front side defect; post laser anneal surface condition characterization; process-design sensitive test chip inspection; reticle re-qualification methods; advanced wafer fabs; automated wafer edge inspection system; IC manufacturing; yield-limiting nano-scale whisker defects; photolithography; EEPROM Cell; SOI analog circuits; surface killer defect detection; crystalline X-ray diffraction for semiconductor metrology; silicon surface roughness impact; power semiconductor devices; SOI-based microprocessor chip; BiCMOS technology wafer storage quality; immersion lithography; drain transistor reliability; shallow trench isolation; DRAM photoresist development analysis; overall equipment productivity; zero defect manufacturing product analysis; yield prediction system; self-align double patterning process; NAND flash cell; microelectronic device manufacturing; and balanced machine workload dispatching scheme.
Keywords :
BiCMOS integrated circuits; DRAM chips; EPROM; NAND circuits; analogue integrated circuits; annealing; immersion lithography; integrated circuit layout; integrated circuit manufacture; integrated circuit testing; microprocessor chips; nanoelectronics; photoresists; power semiconductor devices; reticles; semiconductor device reliability; silicon; silicon-on-insulator; surface roughness; BiCMOS Technology; DRAM; E-beam inspection methodology; EEPROM cell; IC layouts proximity correction; IC manufacturing; NAND flash cell; SOI analog circuits; SOI-based microprocessor chip; advanced wafer fabs; automated wafer edge inspection system; balanced machine workload dispatching scheme; embedded mechanical stress sensors; immersion lithography; lateral extended drain transistor reliability; linear semiconductor manufacturing logistics; microelectronic device manufacturing; model-based layout optimization; overall equipment productivity analysis; photolithography; photoresist development; post laser anneal surface condition characterization; power semiconductor devices; process-design sensitive test chips inspection; product yield prediction system; reticle re-qualification methods; self-align double patterning process; semiconductor metrology; shallow trench isolation; silicon lattice damage measurement; silicon surface roughness impact; surface killer defect detection; wafer damage induced wafer front side defect; wafer storage quality; yield-limiting nanoscale whisker defects; zero defect manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI
Conference_Location :
Stresa
Print_ISBN :
1-4244-0652-8
Type :
conf
DOI :
10.1109/ASMC.2007.375054
Filename :
4259220
Link To Document :
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