Title :
Simulations of CMOS circuit degradation due to hot-carrier effects
Author :
Quader, Khandker N. ; Ko, Ping K. ; Hu, Chenming ; Fang, Peng ; Yue, John T.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
March 31 1992-April 2 1992
Abstract :
By comparing long-term ring-oscillator hot-carrier degradation data and simulation results the authors show that a public-domain circuit simulator, BERT (Berkeley Reliability Tools), can predict CMOS digital circuit speed degradation from transistor DC stress data. Large initial PMOSFET drain current enhancement can result in initial frequency enhancement followed by an initial fast degradation due to the zero crossing effect. The relationship between circuit lifetime and transistor DC stress is examined.<>
Keywords :
CMOS integrated circuits; circuit reliability; digital integrated circuits; hot carriers; integrated circuit testing; semiconductor process modelling; 0.7 micron; BERT; CMOS circuit degradation; LDD CMOS technology; PMOSFET drain current enhancement; circuit lifetime; digital circuit speed degradation; frequency enhancement; hot-carrier degradation; public-domain circuit simulator; ring-oscillator; simulation; transistor DC stress data; zero crossing effect; Bit error rate; CMOS digital integrated circuits; Circuit simulation; Degradation; Digital circuits; Hot carrier effects; Hot carriers; MOSFET circuits; Predictive models; Stress;
Conference_Titel :
Reliability Physics Symposium 1992. 30th Annual Proceedings., International
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-0473-X
DOI :
10.1109/RELPHY.1992.187616
