DocumentCode :
2922114
Title :
Metal Hardmask Etch Residue Removal For Advanced Copper / Low-k Devices
Author :
Cui, Hua ; Kirk, Simon J. ; Maloney, David
Author_Institution :
EKC Technol. DuPont Electron. Technol., Barrington
fYear :
2007
fDate :
11-12 June 2007
Firstpage :
366
Lastpage :
370
Abstract :
Plasma dry etching processes are commonly used to fabricate vertical sidewall trenches and vias for copper (Cu)/low-k dual damascene devices. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the dry etching process in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Other particulate etch residues (such as mixtures of copper oxide (CuxOy) with polymers) can be seen in the bottom of the vias. As technology nodes advance to 45 nm and beyond, IC companies are investigating the use of a metal hardmask such as TiN in order to gain better etching selectivity to the low-k materials during the dry etching process. In order to obtain reliable, low-resistance interconnects that can be used to manufacture advanced IC devices, the polymers on the sidewalls and the particulate residues at the via bottoms must be removed prior to the next process step. In this paper we report a recently developed wet cleaning approach to remove the metal hardmask etch residues while maintaining high selectivity to the copper and low-k film(s). This was demonstrated at the 45 nm technology node for porous low-k, as well as 65 nm for non-porous low-k materials through controlled modification of the formulations. The cleaning mechanism of the etch residues is discussed.
Keywords :
copper; integrated circuit interconnections; low-k dielectric thin films; plasma materials processing; porous materials; semiconductor device manufacture; semiconductor device models; semiconductor device reliability; sputter etching; titanium compounds; Cu; TiN; advanced IC device manufacture; copper-low-k dual damascene devices; low-resistance interconnects; metal hardmask etch residue removal; nonporous low-k materials; particulate etch residues; plasma dry etching process; porous low-k materials; size 45 nm; size 65 nm; vertical sidewall trench fabrication; wet cleaning approach; Cleaning; Copper; Dry etching; Inorganic materials; Manufacturing processes; Plasma applications; Plasma devices; Polymers; Protection; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI
Conference_Location :
Stresa
Print_ISBN :
1-4244-0652-8
Electronic_ISBN :
1-4244-0653-6
Type :
conf
DOI :
10.1109/ASMC.2007.375065
Filename :
4259231
Link To Document :
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