DocumentCode
2922293
Title
Geometry effects on the NBTI degradation of PMOS transistors
Author
Math, Gaetan ; Benard, Christelle ; Ogier, Jean-Luc ; Goguenheim, Didier
Author_Institution
ST Microelectron., Zone Ind. Rousset, Rousset
fYear
2008
fDate
12-16 Oct. 2008
Firstpage
60
Lastpage
63
Abstract
This paper presents the real impact of transistor geometry on the NBTI degradation. IDsat degrades faster longer transistors, which is attributed to the small relative saturation region with respect to the total channel length. Narrow transistor degradation is accelerated by the contribution of the edge of the active region. Transistor lifetime depends on their width in a logarithmic way. It also explain the instability observed in measurements on small area transistors by the impact of very few defects relaxation during the measurements. Low voltage P-channel MOSFETs with various channel lengths and widths are used in this study. According to this work, the worst case for NBTI degradation would be a narrow and long transistor.
Keywords
MOSFET; geometry; semiconductor device reliability; PMOS transistors; narrow transistor degradation; negative bias temperature instability degradation; transistor geometry; Condition monitoring; Degradation; Geometry; MOSFET circuits; Microelectronics; Negative bias temperature instability; Niobium compounds; Stress; Threshold voltage; Titanium compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International
Conference_Location
S. Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-2194-7
Electronic_ISBN
1930-8841
Type
conf
DOI
10.1109/IRWS.2008.4796087
Filename
4796087
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