Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm

In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions.