Accelerated 65nm Yield Ramp through Optimization of Inspection on Process-Design Sensitive Test Chips

This paper describes an integrated methodology that combines short-flow test chips useful for exploring process-design systematic as well as random failure modes and an advanced inspection tool platform to characterize and monitor key Defects-of-Interest for accelerated defect-based yield learning at the 65 nm technology node. Utilization of a unique fast electrical testing scheme, rapid analysis software along with optimized inspection facilitated shorter learning cycles for accelerated process development. Knowledge derived from the CVreg- based inspection setup in a leading 300 mm fab was successfully transferred to manufacturing to facilitate inspection optimization for key Defects-of-Interest on product wafers.