A Low Power Folded Mixer Using Even Harmonic Technology

Author

Weng, Ro-Min ; Wang, Jing-Chyi ; Li, Shu-Ya ; Wei, Hung-Che

Author_Institution

Nat. Dong Hwa Univ., Hualien

fYear

2007

fDate

9-11 Dec. 2007

Firstpage

247

Lastpage

249

Abstract

A CMOS down-conversion folded mixer for the radio frequency (RF) applications is presented. The proposed mixer composes of frequency doubling circuits, transconductance stages, and folded switching stages. With input 1.9 GHz RF signals of -40 dBm driven by 0.948 GHz local oscillation (LO) signals of 0 dBm, the mixer shows a good performance in both the high linearity and the low power consumption. The third-order input intercept point (IIP3) and the power consumption including the buffer stage are -3dBm and 6.4mW, respectively. The proposed mixer is designed and fabricated by tsmc 0.18mum 1P6M CMOS process with the size of 0.989 x 0.559mm².

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF mixers; low-power electronics; CMOS down-conversion folded mixer; even harmonic technology; folded switching stages; frequency 0.948 GHz; frequency 1.9 GHz; frequency doubling circuits; local oscillation signals; low power consumption; low power folded mixer; power 6.4 mW; radio frequency; size 0.18 mum; third-order input intercept point; transconductance stages; CMOS process; CMOS technology; Energy consumption; Linearity; Power system harmonics; RF signals; Radio frequency; Radiofrequency integrated circuits; Switching circuits; Transconductance; IIP3; Mixer; RF; front-end; receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on

Conference_Location

Rasa Sentosa Resort

Print_ISBN

978-1-4244-1307-2

Electronic_ISBN

978-1-4244-1308-9

Type

conf

DOI

10.1109/RFIT.2007.4443962

Filename

4443962