Dynamic gate coupling of NMOS for efficient output ESD protection

Author

Duvvury, Charvaka ; Diaz, Carlos

Author_Institution

Texas Instruments Inc., Dallas, TX, USA

fYear

1992

fDate

March 31 1992-April 2 1992

Firstpage

141

Lastpage

150

Abstract

A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed.<>

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; electrostatic discharge; insulated gate field effect transistors; integrated circuit technology; integrated logic circuits; overvoltage protection; CMOS; ESD transient conditions; MOSIC; NMOS output devices; NMOS transistors; design issues; device operation; dynamic gate coupling effect; dynamic gate-coupled device; gate coupling phenomenon; measured ESD stress; modeling results; nonsilicided devices; operation; optimisation; output ESD protection; silicided structures; simulation results; CMOS technology; Degradation; Electric breakdown; Electrostatic discharge; Logic devices; MOS devices; MOSFET circuits; Protection; Substrates; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium 1992. 30th Annual Proceedings., International

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-0473-X

Type

conf

DOI

10.1109/RELPHY.1992.187639

Filename

187639