A dynamic way cache locking scheme to improve the predictability of power-aware embedded systems

Cache memory challenges the power supply system by consuming a lot of power. Cache also increases execution time unpredictability and makes it difficult to support real-time applications. Recent studies indicate that way cache locking can be applied in embedded systems to improve predictability (and performance/power ratio). In this work, we propose a simple but effective dynamic way cache locking scheme for embedded systems which is effective for both single-core and multicore systems. This scheme is based on the analysis of applications´ worst case execution time (WCET) and it allows changing the locked cache size during runtime to achieve the optimal predictability and performance/power ratio for the running application. Using Heptane WCET analyzer, we study MPEG4, FFT, MI, and DFT codes and generate workloads. Workloads provide miss information for the memory blocks (without cache locking). Using VisualSim tool, we model and simulate a system with four cores and two levels of caches. Experimental results show that our cache locking scheme significantly improves predictability by decreasing total misses more than 50%. It is also observed that predictability can be improved even further by locking more than 25% of the cache size at the expense of performance/power ratio.