Title :
A Robust Single Event Upset Hardened Clock Distribution Network
Author :
Mallajosyula, Aahlad ; Zarkesh-Ha, Payman
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of New Mexico, Albuquerque, NM
Abstract :
Single event upset along with the technology scaling decreases the reliability of the present CMOS circuits. It has recently been shown that the clock distribution network is becoming increasingly vulnerable to single event upset. In this paper a new technique is proposed, that can eliminate more than 90% of SEU in clock distribution network. The proposed technique incurs minimal area overhead and requires negligible design effort.
Keywords :
CMOS integrated circuits; clocks; integrated circuit reliability; radiation hardening (electronics); CMOS integrated circuit reliability; clock distribution network; single event upset; Clocks; Delay; Driver circuits; Error analysis; Filters; Flip-flops; Jitter; Radiation hardening; Robustness; Single event upset;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International
Conference_Location :
S. Lake Tahoe, CA
Print_ISBN :
978-1-4244-2194-7
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2008.4796101
