DocumentCode :
2922728
Title :
Measurement Issues for High-k Technology including NBTI
Author :
Young, Cliff
Author_Institution :
SEMATECH, Austin, TX
fYear :
2008
fDate :
12-16 Oct. 2008
Firstpage :
145
Lastpage :
145
Abstract :
This tutorial was comprised of several parts that address various measurement methodologies required for properly characterizing high-k gate stacks. While discussing these techniques, emphasis was placed on proper instrumentation and set up, followed by proper data analysis and interpretation. Some of the key methodologies that were discussed are: capacitance-voltage (C-V), pulsed current-voltage (1-V), and reliability evaluation techniques. The intended outcome of this tutorial was for the attendees to leave with a better understanding of high-k characterization requirements that he/she can implement in everyday measurements and have increased insight about these novel gate stacks.
Keywords :
integrated circuit reliability; integrated circuit technology; capacitance-voltage; data analysis; data interpretation; high-k gate stacks; measurement methodologies; pulsed current-voltage; reliability evaluation techniques; Circuit testing; Data analysis; Dispersion; High K dielectric materials; High-K gate dielectrics; Negative bias temperature instability; Niobium compounds; Predictive models; Semiconductor device modeling; Titanium compounds;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International
Conference_Location :
S. Lake Tahoe, CA
ISSN :
1930-8841
Print_ISBN :
978-1-4244-2194-7
Electronic_ISBN :
1930-8841
Type :
conf
DOI :
10.1109/IRWS.2008.4796108
Filename :
4796108
Link To Document :
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