DocumentCode
2923136
Title
Positive Bias Temperature Instability Effects in advanced High-k / Metal Gate NMOSFETs
Author
Ioannou, Dimitris P. ; Mittl, Steve ; LaRosa, Giuseppe
Author_Institution
IBM Microelectronics, Semiconductor R&D Center, Essex Junction, VT
fYear
2008
fDate
12-16 Oct. 2008
Abstract
This article consists of a collection of slides from the author´s conference presentation. Some of the specific areas/topics discussed include: Introduction; Fast switching modular level (long term) based PBTI characterization for accurate lifetime projections; Effect of stress voltage on time dependency; Effect of stress voltage on Temperature activation SILC effects; Gated diode measurements; Effect of high-k layer thickness; Physicals insights and preliminary models; and a Summary.
Keywords
Acceleration; Degradation; High K dielectric materials; High-K gate dielectrics; MOSFETs; Stress measurement; Temperature dependence; Thickness measurement; Time measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International
Conference_Location
S. Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-2194-7
Type
conf
DOI
10.1109/IRWS.2008.4796131
Filename
4796131
Link To Document