Title :
A 52-mW 8.29mm2 19-mode LDPC decoder chip for Mobile WiMAX applications
Author :
Shih, Xin-Yu ; Zhan, Cheng-Zhou ; Lin, Cheng-Hung ; Wu, An-Yeu Andy
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
This paper presents a LDPC decoder chip supporting all 19 modes in mobile WiMAX applications. An efficient IC design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. In addition, we propose a new early termination scheme that can dynamically adjust the iteration number. The multi-mode chip implemented in 8.29 mm2 die area can be maximally measured at 83.3 MHz with only 52 mW power consumption.
Keywords :
WiMax; decoding; iterative methods; mobile radio; parity check codes; LDPC decoder chip; decoding latency; efficient IC design strategy; frequency 83.3 MHz; hardware utilization ratio; iteration number; mobile WiMAX applications; Delay; Energy consumption; Hardware; Iterative decoding; Parity check codes; Power measurement; Reconfigurable architectures; Routing; Semiconductor device measurement; WiMAX;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796462
