• DocumentCode
    2925756
  • Title

    Exploring adjacency in floorplanning

  • Author

    Wang, Jia ; Zhou, Hai

  • Author_Institution
    Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
  • fYear
    2009
  • fDate
    19-22 Jan. 2009
  • Firstpage
    367
  • Lastpage
    372
  • Abstract
    This paper describes a new floorplanning approach called constrained adjacency graph (CAG) that helps exploring adjacency in floorplans. CAG extends the previous adjacency graph approaches by adding explicit adjacency constraints to the graph edges. After sufficient and necessary conditions of CAG are developed based on dissected floorplans, CAG is extended to handle general floorplans in order to improve area without changing the adjacency relations dramatically. These characteristics are currently utilized in a randomized greedy improvement heuristic for wire length optimization. The results show that better floorplans are found with much less running time for problems with 100 to 300 modules in comparison to a simulated annealing floorplanner based on sequence pairs.
  • Keywords
    circuit layout; directed graphs; greedy algorithms; randomised algorithms; simulated annealing; CAG; constrained adjacency graph; floorplanning; randomized greedy improvement heuristic; simulated annealing floorplanner; wire length optimization; Binary sequences; Circuit topology; Cost function; Design optimization; Intellectual property; Iterative algorithms; Simulated annealing; Tree graphs; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    978-1-4244-2748-2
  • Electronic_ISBN
    978-1-4244-2749-9
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2009.4796508
  • Filename
    4796508