DocumentCode :
2925827
Title :
Noise minimization during power-up stage for a multi-domain power network
Author :
Zhang, Wanping ; Zhu, Yi ; Yu, Wenjian ; Shayan, Amirali ; Wang, Renshen ; Zhu, Zhi ; Cheng, Chung-Kuan
Author_Institution :
Qualcomm Inc., San Diego, CA
fYear :
2009
fDate :
19-22 Jan. 2009
Firstpage :
391
Lastpage :
396
Abstract :
With the popularity of multiple power domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficient heuristic algorithm to arrange the power-up sequence in a multi-domain power network in order to minimize the noise. We present a formulation of this problem and show it is NP-complete. Therefore, we propose a simulated annealing (SA) based algorithm with preprocessing. Experimental results show that the proposed algorithm can minimize the noise close to the minimal values. In terms of efficiency, the SA algorithm is more than hundreds of times faster than the enumerating method and the running time scales well for these cases with the number of domains. In addition, we discuss the trade off between power-up efficiency and noise.
Keywords :
interference suppression; power supplies to apparatus; simulated annealing; NP-complete; heuristic algorithm; multidomain power network noise analysis; multidomain power network noise minimization; multidomain power network power-up stage; simulated annealing; Algorithm design and analysis; Circuit noise; Logic circuits; Logic gates; Minimization; Noise level; Power supplies; Simulated annealing; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
Type :
conf
DOI :
10.1109/ASPDAC.2009.4796512
Filename :
4796512
Link To Document :
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