A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Author

Mehdipour, Farhad ; Noori, Hamid ; Javadi, Bahman ; Honda, Hiroaki ; Inoue, Koji ; Murakami, Kazuaki

Author_Institution

Fac. of Inf., Sci. & Electr. Eng., Kyushu Univ., Fukuoka

fYear

2009

fDate

19-22 Jan. 2009

Firstpage

564

Lastpage

569

Abstract

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

Keywords

instruction sets; microprocessor chips; performance evaluation; reduced instruction set computing; combined analytical and simulation-based model; cycle-accurate simulation; performance evaluation; reconfigurable instruction set processor; Analytical models; Computational Intelligence Society; Computational modeling; Computer simulation; Design optimization; Information analysis; Information science; Information technology; Java; Performance analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

978-1-4244-2748-2

Electronic_ISBN

978-1-4244-2749-9

Type

conf

DOI

10.1109/ASPDAC.2009.4796540

Filename

4796540