Title :
High-performance global routing with fast overflow reduction
Author :
Chen, Huang-Yu ; Hsu, Chin-Hsiung ; Chang, Yao-Wen
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enhanced iterative negotiation-based rip-up/rerouting (INR). The prerouting employs a two-stage technique of congestion-hotspot historical cost pre-increment followed by small bounding-box area routing. The initial routing is based on efficient iterative monotonic routing. For traditional INR, it has evolved as the main stream for the state-of-the-art global routers, which reveals its great ability to reduce the congestion and overflow. As pointed out by recent works, however, traditional INR may get stuck at local optima as the number of iterations increases. To remedy this deficiency, we replace INR by enhanced iterative forbidden-region rip-up/rerouting (IFR) which features three new techniques of (1) multiple forbidden regions expansion, (2) critical subnet rerouting selection, and (3) look-ahead historical cost increment. Experimental results show that NTUgr achieves high-quality results for the ISPD´07 and ISPD´08 benchmarks for both overflow and runtime.
Keywords :
VLSI; integrated circuit design; network routing; NTUgr; bounding-box area routing; critical subnet rerouting selection; high-performance global routing; iterative negotiation-based rip-up rerouting; look-ahead historical cost increment; multiple forbidden regions expansion; overflow reduction; Circuit synthesis; Convergence; Costs; Design engineering; History; Integer linear programming; Lagrangian functions; Routing; Runtime; Tiles;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796543