Title :
RF-analog circuit design in scaled SoC
Author :
Itoh, Nobuyuki ; Hamada, Mototsugu
Author_Institution :
Semicond. Co., Toshiba Corp., Yokohama
Abstract :
Downscaling of process technology increases the development cost of RFCMOS SoC. Therefore, designers have to minimize the number of respins, and have to try to obtain higher yield. RFCMOS SoC consists of RF-analog, mixed-signal, logic and memory circuits. In order to realize a small number of respins number and higher yield, key issues are robust design methodology of RF-analog circuits, and full-chip verification. This paper describes practical techniques corresponding to those issues.
Keywords :
CMOS analogue integrated circuits; integrated circuit design; integrated circuit yield; logic circuits; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; system-on-chip; RF-analog circuit design; RFCMOS SoC; full-chip verification; logic circuits; memory circuits; mixed-signal circuits; respins number; yield; Analog circuits; Built-in self-test; Circuit simulation; Circuit synthesis; Digital systems; Logic circuits; MOSFETs; Radio frequency; Signal design; System analysis and design;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796562
