Title :
Improved performance and resource usage of FPGA using resource-aware design; the case of a decimal array multiplier
Author :
Hosseiny, Adel ; Amanollahi, Saba ; Hashemi, Reza ; Jahanian, A.
Author_Institution :
Dept. of Comput. & Electr. Eng., Shahid Beheshti Univ., Tehran, Iran
Abstract :
Awareness of the available resources in FPGA platform can improve the quality of the hardware design. Decimal array multipliers due to their regular nature and compatibility with the CLB structure of FPGA platform are suitable cases to this aim. In this paper, PPG unit of a decimal multiplier has been realized using two different approaches in order to improve utilization of the FPGA resources.
Keywords :
field programmable gate arrays; logic design; multiplying circuits; CLB structure; FPGA platform; decimal array multiplier; hardware design; resource-aware design; Algorithm design and analysis; Arrays; Computers; Delays; Field programmable gate arrays; Hardware; Table lookup; Decimal Array Multiplier; FPGA; Resource-aware design;
Conference_Titel :
Computer Architecture and Digital Systems (CADS), 2013 17th CSI International Symposium on
Conference_Location :
Tehran
Print_ISBN :
978-1-4799-0562-1
DOI :
10.1109/CADS.2013.6714248
