Design and performance evaluation of a low cost Full Protected CMOS Latch

As the density of modern VLSI circuits increases, the supply voltage and gate capacitances decrease. This has led to high vulnerability to radiation induced transient faults in nanoscale CMOS circuits. This paper proposes an efficient robust latch design in 45 nm CMOS technology. The proposed latch prevents propagating transient pulses occurred in the input node with no extra delay and protects the data stored by using redundant internal nodes. Hspice simulation reveals that the proposed design provides full protection with 32% lower power consumption and 24% lower power delay product compared to the conventional reference latch.