Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V_t, as well as strongly affects mobility, N_it and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V_t tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO₂) IL. T_inv=1.15 nm and V_t,lin=0.31 V was obtained while achieving the following attributes: mobility~70%, N_it <5times10¹⁰ cm^-2, DeltaV_t<30 m V within wafer, BTI DeltaV_t <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.