High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

Author

Packan, P. ; Cea, S. ; Deshpande, H. ; Ghani, T. ; Giles, M. ; Golonzka, O. ; Hattendorf, M. ; Kotlyar, R. ; Kuhn, K. ; Murthy, A. ; Ranade, P. ; Shifren, L. ; Weber, C. ; Zawadzki, K.

Author_Institution

Logic Technol. Dev., Process Technol. Modeling Intel Corp., Hillsboro, OR

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

Keywords

MOSFET; elemental semiconductors; semiconductor device reliability; silicon; (110) silicon substrates; 2D short channel effects; NMOS performance; Si; device reliability; hi-k + metal gate strain; size 45 nm; voltage 1 V; Capacitive sensors; Charge carrier processes; Compressive stress; Degradation; Electron mobility; High K dielectric materials; High-K gate dielectrics; MOS devices; Occupational stress; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796614

Filename

4796614