DocumentCode
292815
Title
Multiport memory based data path allocation focusing on interconnection optimization
Author
Jou, Jer-Min ; Chen, Ren-Der ; Kuang, Shiann-Rong
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
45
Abstract
A method based on the 0-1 integer linear programming (ILP) model aiming primarily at minimizing the cost of interconnections is proposed for solving the data path allocation problem using multiport memories. The interconnection elements are generally composed of buses, multiplexers, and tri-state buffers. After solving the operation binding problem, we first find the number of buses required. Then we deal with the multiport memory allocation problem simultaneously minimizing the cost of multiplexers and tri-state buffers. From the solution quality and execution time of the experimental results, we see that our method is suitable for solving data path allocation problem using multiport memories when the cost of interconnections is first considered
Keywords
circuit layout CAD; circuit optimisation; integer programming; integrated circuit interconnections; integrated circuit layout; linear programming; logic CAD; minimisation of switching nets; 0-1 integer linear programming; ILP model; data path allocation; interconnection optimization; multiport memory based method; operation binding problem; Clocks; Cost function; High level synthesis; Integer linear programming; Integrated circuit interconnections; Minimization; Multiplexing; Registers; Resource management; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408751
Filename
408751
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