DSP system synthesis including variable data path width

This paper presents a high-level synthesis methodology which may be applied to the synthesis of bit-serial, digit-serial or bit-parallel digital signal processing (DSP) systems. The methodology accepts as input a DSP system behavioral specification. The methodology provides for the optimization of DSP systems subject to constraints on throughput, IC area, data path width, and resource sharing strategies. The optimization technique is based on a generalized hill climbing algorithm known as simulated annealing. The output is control logic and data path specifications in a device independent hardware description language. Design examples of bit-serial and digit-serial filter realizations synthesized using the methodology are included