The impact of la-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions

Author

Kang, C.Y. ; Young, C.D. ; Huang, J. ; Kirsch, P. ; Heh, D. ; Sivasubramani, P. ; Park, H.K. ; Bersuker ; Lee, B.H. ; Choi, H.S. ; Lee, K.T. ; Jeong, Y.H. ; Lichtenwalner, J. ; Kingon, A.I. ; Tseng, H.-H. ; Jammy, R.

Author_Institution

SEMATECH, Austin, TX

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

La-doped HfSiO samples show lower threshold voltage (V_th) and gate current (I_gate), which is attributed to dipole formation at the high-k/SiO₂ interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater barrier offset. However, the primary cause for defect generation at high field stress is attributed to the La atoms in the interfacial SiO₂ layer. By optimizing the technique to incorporate nitrogen into the bottom interface, this high field reliability issue can be minimized while maintaining good device characteristics.

Keywords

MOSFET; doping; hafnium compounds; lanthanum; semiconductor device reliability; silicon compounds; HfSiO:La; charge trapping efficiency; defect generation; dipole formation; gate current; gate stress; greater barrier offset; metal gate nMOSFET; positive bias temperature instability; Atomic layer deposition; Degradation; Doping; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFETs; Stress control; Temperature control; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796628

Filename

4796628