DocumentCode
292824
Title
A redefinable symbolic simulation technique to testability design rules checking
Author
Hirech, M. ; Florent, O. ; Greiner, A. ; Rejouan, E.
Author_Institution
Paris VI Univ., France
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
89
Abstract
Symbolic simulation approach is well suited for VLSI design for testability (DFT) rules checking. Unfortunately the existing techniques are not extensible and therefore the verification tools based on them can not be parametrized to follow the evolution of rules. As a solution, a concept of symbolic simulator generator is proposed: both symbolic values and transfer functions of gates are redefinable to cope with different sets of rules and design methodologies
Keywords
VLSI; circuit analysis computing; design for testability; logic CAD; transfer functions; VLSI; design for testability; design methodologies; redefinable symbolic simulation technique; symbolic values; testability design rules checking; transfer functions; verification tools; Circuit simulation; Circuit testing; Clocks; Computational modeling; Design for testability; Design methodology; Gold; Shift registers; Transfer functions; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408762
Filename
408762
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