DocumentCode
292830
Title
Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles
Author
Ganley, Joseph L. ; Cohoon, James P.
Author_Institution
Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
113
Abstract
This paper presents a new model for VLSI routing in the presence of obstacles, that transforms any routing instance from a geometric problem into a graph problem. It is the first model that allows computation of optimal obstacle-avoiding rectilinear Steiner trees in time corresponding to the instance size (the number of terminals and obstacle border segments) rather than the size of the routing area. For the most common multi-terminal critical nets-those with three or four terminals-we observe that optimal trees can be computed as efficiently as good heuristic trees, and present algorithms that do so. For nets with five or more terminals, we present algorithms that heuristically compute obstacle-avoiding Steiner trees. Analysis and experiments demonstrate that the model and algorithms work well in both theory and practice
Keywords
VLSI; circuit layout CAD; graph theory; integrated circuit layout; multiterminal networks; network routing; network topology; trees (mathematics); Steiner tree construction; VLSI routing; graph problem; heuristic trees; multi-terminal critical net; obstacle border segments; obstacle-avoiding rectilinear trees; routing instance; Algorithm design and analysis; Computational modeling; Computer science; Design automation; Logic; Polynomials; Routing; Solid modeling; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408768
Filename
408768
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