Architecture of a highly reliable systolic correlator array

The architecture of a highly reliable systolic correlator array which forms part of a family of devices sharing a common cell architecture is outlined. The design of the cell is novel, and the reliability characteristics are scalable across the family to provide defect and fault tolerance. This is achieved by using an interconnection harness, which effectively straps or links only the healthy cells of the array into a working structure. The correlator array is designed to operate at a constant throughput rate, allowing a dynamic selection of the precision of correlation coefficients. A tradeoff between the precision of coefficients and latency of the array, as well as between the precision of coefficients and size of the correlation template, is possible. This makes the family of devices highly flexible and suited for a wide range of applications