• DocumentCode
    292840
  • Title

    A new approach to floorplan area optimization: to slice or not to slice?

  • Author

    Chen, Cheng-Hsi ; Tollis, Ioannis G.

  • Author_Institution
    Dept. of Comput. Sci., Texas Univ., Dallas, TX, USA
  • Volume
    1
  • fYear
    1994
  • fDate
    30 May-2 Jun 1994
  • Firstpage
    161
  • Abstract
    We consider the problem of minimizing the area of a given floorplan by slightly changing its topology and present algorithms for solving it. Our algorithms are very efficient and the results compare favorably with the optimal solutions of the original floorplans. Specifically, we concentrate on converting spiral floorplans into slicing floorplans such that the area is minimized. Naturally, the cyclic channel precedence constraints disappear, which implies that the routing phase will be easier and will require less area. Surprisingly, our experimental results show that in most cases, this conversion is very good with respect to the area of the original spiral floorplan. Namely, the resulting slicing floorplans are smaller than the corresponding spiral floorplans
  • Keywords
    VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; minimisation; network topology; VLSI layout; area minimization; cyclic channel precedence constraints; floorplan area optimization; slicing floorplans; spiral floorplans; Circuits; Computer science; Design optimization; Process design; Routing; Spirals; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
  • Conference_Location
    London
  • Print_ISBN
    0-7803-1915-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1994.408780
  • Filename
    408780