DocumentCode :
292842
Title :
Interior point methods for placement
Author :
Chin, P. ; Vannelli, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume :
1
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
169
Abstract :
In VLSI layout optimization, the placement problem is usually solved with simulated annealing or heuristic algorithms. These procedures often begin with random initial configurations but may benefit greatly (in terms of execution time or quality of solution) when good initial relative placements are provided. Weis and Mlynski [1987] have presented a linear programming formulation for generating relative placements. In this paper, we show how efficient interior point and preconditioned conjugate gradient methods can be applied to solve large sparse linear programs based on Weis and Mlynski´s approach
Keywords :
VLSI; cellular arrays; circuit layout CAD; circuit optimisation; conjugate gradient methods; linear programming; logic CAD; logic arrays; simulated annealing; VLSI layout optimization; gate arrays; heuristic algorithms; initial relative placements; interior point methods; large sparse linear programs; placement problem; preconditioned conjugate gradient methods; simulated annealing; standard cells; Computational modeling; Computer simulation; Ear; Gradient methods; Heuristic algorithms; Law; Log periodic antennas; Optimization methods; Simulated annealing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.408782
Filename :
408782
Link To Document :
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