Title :
A systolic graph partitioning algorithm for VLSI design
Author :
Wakabayashi, Shin´ichi ; Isomoto, Kazunori ; Koide, Tetsushi ; Yoshida, Noriyoshi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
fDate :
30 May-2 Jun 1994
Abstract :
The graph partitioning problem is to partition the vertices of an undirected graph G=(V, E) into two sets of equal size such that the number of edges between them is minimized. In this paper, we propose a systolic algorithm for graph partitioning. The algorithm is based on the Kernighan-Lin heuristic algorithm, runs on a linear array consisting of O(|V|) processing units, and is very suitable for direct VLSI implementation. Computation time of one pass of the proposed algorithm is O(|V|). Simulation experiments showed that the proposed algorithm is as good as the original KL heuristic
Keywords :
VLSI; circuit CAD; computational complexity; graph theory; integrated circuit design; parallel algorithms; Kernighan-Lin heuristic algorithm; VLSI design; computation time; linear array; systolic graph partitioning algorithm; undirected graph; Algorithm design and analysis; Circuit simulation; Computational modeling; Costs; Heuristic algorithms; Logic design; Parallel algorithms; Partitioning algorithms; Very large scale integration; Virtual reality;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408796
