Implementation of video codec with programmable parallel DSP

Author

Nomura, M. ; Suzuki, Jun ; Ono, Shintaro

Author_Institution

NTT Transmission Syst. Lab., Kanagawa

fYear

1989

fDate

27-30 Nov 1989

Firstpage

908

Abstract

The implementation of a video codec with a programmable parallel digital signal processor (DSP) is described. The advantages of DSP implementation over dedicated VLSI implementation are discussed. System design concepts and the architecture for a multicomputer-type DSP system called NOVI are reviewed. This system has been developed as a prototype for program development and performance evaluation of parallel processing systems. Intraframe DCT (discrete cosine transform) codec is implemented by NOVI as an example of a transform-type video codec. The processing speed of the implemented codec is examined. This codec can process 9 frames/s (one frame consists of a 256×240 pixel image) using 34 PEs (processing elements): 16 PEs for the coder, 16 PEs for the decoder, and 2 PEs for the video I/O. Packet assembly and multiplexing are also performed by the codec

Keywords

codecs; computerised picture processing; digital signal processing chips; multiprocessor interconnection networks; parallel processing; transforms; video signals; 240 pixels; 256 pixels; 61440 pixels; NOVI; coder; decoder; intraframe DCT codec; multicomputer-type DSP system; processing elements; processing speed; programmable parallel DSP; system design concept; video I/O; video codec; Assembly; Decoding; Digital signal processing; Digital signal processors; Discrete cosine transforms; Parallel processing; Pixel; Prototypes; Very large scale integration; Video codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference and Exhibition 'Communications Technology for the 1990s and Beyond' (GLOBECOM), 1989. IEEE

Conference_Location

Dallas, TX

Type

conf

DOI

10.1109/GLOCOM.1989.64093

Filename

64093