Iterated timing analysis with dynamic partitioning technique for bipolar transistor circuits

Author

Ishida, Masaki ; Nishigaki, Masakatsu ; Hayashi, Koichi ; Asai, Hideki

Author_Institution

Fac. of Eng., Shizuoka Univ., Hamamatsu, Japan

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

411

Abstract

This paper presents relaxation-based algorithms with the dynamic partitioning technique for bipolar circuit analysis. In this technique, a circuit is partitioned dynamically based on the consideration of the operating region of specified bipolar devices throughout the simulation interval. This technique has been used already in the waveform relaxation method, and, in this paper, is implemented in the Iterated Timing Analysis (ITA). The present method is applied to the transient simulation of several digital bipolar junction transistor (BJT) circuits and compared with the waveform relaxation method

Keywords

bipolar digital integrated circuits; circuit analysis computing; iterative methods; timing; bipolar transistor circuits; digital circuits; dynamic partitioning technique; iterated timing analysis; relaxation-based algorithms; transient simulation; Algorithm design and analysis; Bipolar transistor circuits; Circuit analysis; Circuit simulation; Convergence; Coupling circuits; Heuristic algorithms; Partitioning algorithms; Relaxation methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408826

Filename

408826